In dynamic random access memory (DRAM) fabrication technology, continuous efforts are being made to build a capacitor of larger capacitance in a smaller space.
FIGS. 1(A)-(C) illustrate one of the conventional techniques for forming a DRAM capacitor. The fabrication process of such a DRAM capacitor will be explained briefly below.
As shown in FIG. 1(A), after forming necessary elements on semiconductor substrate 1, the overall surface is coated with insulation layer 2. A contact hole for making contact between a source/drain region in semiconductor substrate 1 (not explicitly shown) and a capacitor electrode is formed by application of a photolithographic or photo-etching process to predetermined portions of insulating layer 2. Continually, doped polysilicon is deposited by a low pressure chemical vapor deposition (LPCVD) process at a temperature of about 600.degree. C., and a portion of a capacitor storage node is patterned.
Thereafter, as shown in FIG. 1(B), hemispherical polysilicon layer 4 (which has many hemispherical domes on the surface) is deposited under the conditions of pressure of about 1.0 torr, at a temperature of about 550.degree. C., and an ambience of SiH.sub.4 (20%) gas diluted with "He" or helium gas.
A capacitor node is formed by etching back hemispherical polysilicon layer 4, such as by application of a reactive ion etching (dry type of etching) in an atmosphere of "HBr" gas, as illustrated in FIG. 1(C).
Thereafter, the capacitor is fabricated by forming a dielectric layer and a plate electrode of polysilicon.
This conventional method of increasing the surface of the capacitor node by using a hemispherical polysilicon layer typically is insufficient. That is, in the case of a hemispherical polysilicon node compared with a planar node, the increase of the surface area of the node is 2.pi.r.sup.2 /.pi.r.sup.2 =2; it is up to about 2 at best, and it is impossible to be more.